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Title: Digital design : with an introduction to the verilog HDL, VHDL, and system Verilog / M. Morris Mano, Emeritus Professor of Computer Engineering, California State University, Los Angeles, Michael D. Ciletti, Emeritus Professor of Electrical and Computer Engineering, University of Colorado at Colorado Springs.
Main Entry: Mano, M. Morris, 1927- author.
Ciletti, Michael D., author.
Publisher: Pearson Indian Educations Services,
Publication Date: [2018]
Publication Place: Uttar Pradesh, India :
ISBN: 9789353062019
9353062012
Subject: Electronic digital computers -- Circuits.
Logic circuits.
Logic design.
Digital integrated circuits.
Ordinateurs -- Circuits.
Circuits logiques.
Structure logique.
Circuits int�egr�es num�eriques.
Digital integrated circuits.
Electronic digital computers -- Circuits.
Logic circuits.
Logic design.
Edition: Sixth edition, Indian Subcontinent adaptation.
Contents: 1. Digital Systems and Binary Numbers -- 1.1. Digital Systems -- 1.2. Binary Numbers -- 1.3. Number-Base Conversions -- 1.4. Octal and Hexadecimal Numbers -- 1.5. Complements of Numbers -- 1.6. Signed Binary Numbers -- 1.7. Binary Codes -- 1.8. Binary Storage and Registers -- 1.9. Binary Logic -- 2. Boolean Algebra and Logic Gates -- 2.1. Introduction -- 2.2. Basic Definitions -- 2.3. Axiomatic Definition of Boolean Algebra -- 2.4. Basic Theorems and Properties of Boolean Algebra -- 2.5. Boolean Functions -- 2.6. Canonical and Standard Forms -- 2.7. Other Logic Operations -- 2.8. Digital Logic Gates -- 2.9. Integrated Circuits -- 3. Gate-Level Minimization -- 3.1. Introduction -- 3.2. The Map Method -- 3.3. Four-Variable K-Map -- 3.4. Product-of-Sums Simplification -- 3.5. Don't-Care Conditions -- 3.6. NAND and NOR Implementation -- 3.7. Other Two-Level Implementations -- 3.8. Exclusive-OR Function -- 3.9. Hardware Description Languages (HDLS) -- 3.10. Truth Tables in HDLS
Note continued: 4. Combinational Logic -- 4.1. Introduction -- 4.2. Combinational Circuits -- 4.3. Analysis of Combinational Circuits -- 4.4. Design Procedure -- 4.5. Binary Adder -- Subtractor -- 4.6. Decimal Adder -- 4.7. Binary Multiplier -- 4.8. Magnitude Comparator -- 4.9. Decoders -- 4.10. Encoders -- 4.11. Multiplexers -- 4.12. HDL Models of Combinational Circuits -- 4.13. Behavioral Modeling -- 4.14. Writing a Simple Testbench -- 4.15. Logic Simulation -- 5. Synchronous Sequential Logic -- 5.1. Introduction -- 5.2. Sequential Circuits -- 5.3. Storage Elements: Latches -- 5.4. Storage Elements: Flip-Flops -- 5.5. Analysis of Clocked Sequential Circuits -- 5.6. Synthesizable HDL Models of Sequential Circuits -- 5.7. State Reduction and Assignment -- 5.8. Design Procedure -- 6. Registers and Counters -- 6.1. Registers -- 6.2. Shift Registers -- 6.3. Ripple Counters -- 6.4. Synchronous Counters -- 6.5. Other Counters -- 6.6. HDL Models of Registers and Counters -- 7. Memory and Programmable Logic
Note continued: 7.1. Introduction -- 7.2. Random-Access Memory -- 7.3. Memory Decoding -- 7.4. Error Detection and Correction -- 7.5. Read-Only Memory -- 7.6. Programmable Logic Array -- 7.7. Programmable Array Logic -- 7.8. Sequential Programmable Devices -- 8. Design at the Register Transfer Level -- 8.1. Introduction -- 8.2. Register Transfer Level (RTL) Notation -- 8.3. RTL Descriptions -- 8.4. Algorithmic State Machines (ASMs) -- 8.5. Design Example (ASMD CHART) -- 8.6. HDL Description of Design Example -- 8.7. Sequential Binary Multiplier -- 8.8. Control Logic -- 8.9. HDL Description of Binary Multiplier -- 8.10. Design with Multiplexers -- 8.11. Race-Free Design (Software Race Conditions) -- 8.12. Latch-Free Design (Why Waste Silicon?) -- 8.13. SystemVerilog -- An Introduction -- 9. Asynchronous Sequential Logic -- 9.1. Introduction -- 9.2. Analysis Procedure -- 9.3. Circuits with Latches
Note continued: 9.4. Design Procedure -- 9.5. Reduction of State and Flow Tables -- 9.6. Race-Free State Assignment -- 9.7. Hazards -- 9.8. Design Example -- 10. Digital Integrated Circuits -- 10.1. Introduction -- 10.2. Special Characteristics -- 10.3. Bipolar-Transistor Characteristics -- 10.4. RTL and DTL Circuits -- 10.5. Transistor-Transistor Logic -- 10.6. Emitter-Coupled Logic -- 10.7. Metal-Oxide Semiconductor -- 10.8. Complementary MOS -- 10.9. CMOS Transmission Gate Circuits -- 10.10. Switch-Level Modeling with HDL -- 11. Standard Graphic Symbols -- 11.1. Rectangular-Shaped Symbols -- 11.2. Qualifying Symbols -- 11.3. Dependency Notation -- 11.4. Symbols for Combinatorial Elements -- 11.5. Symbols for Flip-Flops -- 11.6. Symbols for Registers -- 11.7. Symbols for Counters -- 11.8. Symbol for RAM -- Appendix -- Answers to Selected Problems -- Index -- Online Chapter: 12. Laboratory Experiments with Standard ICs and FPGAs.

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	Agency:	Collection:	Item Type:	Status:	Barcode:	Media Type:
	Hashemite Main Library	General	Normal Circulation	On Order	-986186	Book